1. Field
The present disclosure generally relates to synchronizing clock signals in electronic devices, and more particularly, to systems and methods for adaptively determining phase shifts during phase-locking feedback loops.
2. Description of the Related Art
Many electronic devices operate based on clock signals. In some situations, it becomes necessary for one clock signal to be synchronized with another clock signal. Typically, such synchronization is achieved by a feedback scheme, where a delay is provided to one signal repeatedly during multiple cycles until the phase of that signal becomes “locked” with the phase of the other signal. A delay-locked loop (DLL) is an example of such a feedback phase-locking circuit.
In situations where the phase difference is initially large, such synchronization can require a large number of feedback cycles to achieve phase-lock. Such large number of cycles can require longer time to achieve synchronization of clock signals. In many electronic devices such as memory devices, where clock synchronization is performed during device initialization, such long initialization time is typically not desirable.
These and other aspects, advantages, and novel features of the present teachings will become apparent upon reading the following detailed description and upon reference to the accompanying drawings. In the drawings, similar elements have similar reference numerals.